DVT Eclipse IDE and DVT IDE for Visual Studio Code are integrated development environments (IDEs) that significantly improve productivity for design and verification engineers.
This detects a wide variety of common errors on the fly, ranging from simple typos to tricky syntactic and semantic errors in RTL constructs. It is much more efficient to find and fix these errors at the coding stage without having to wait for simulation or synthesis. The IDE offers “quick fix” suggestions for many types of errors. SystemVerilog, Verilog, and VHDL are all supported equally well.
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EXAMPLE 1
If you omit a port connection or miss a necessary item in a sensitivity list, the IDE detects and reports the issue.
EXAMPLE 2
If the assignment left-hand side is smaller than the right-hand side, the IDE will report the truncation.
EXAMPLE 3
If you add a signal but do not connect it fully, the IDE will report that is never read, never written, or both.
This makes it faster to enter and modify RTL code, and it eliminates tedious searches to find exact names. This also accelerates language learning for new users and helps even experienced designers, who may have trouble keeping all the syntax in their heads.
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EXAMPLE 1
If you instantiate a module, the IDE generates the entire instantiation and indicates where user input is required. If you defer completing some details, the IDE can add ‘TODO’ or ‘FIXME’ reminder comments in your RTL code.
EXAMPLE 2
If you type in a partial module or signal name, the IDE presents the options for auto-completion based on existing declarations.
This provides a comprehensive view of how all the blocks fit together, making it easy to trace signals through multiple modules and levels of hierarchy. With its complete knowledge of the design structure, the IDE can offer a range of different views to help you in understanding and modifying the design.
These make it much easier to understand your design, especially when some portions are IP blocks or code inherited from other chip projects. The views are synchronized and hyperlinked, with breadcrumbs so you always know where you are in the design hierarchy.
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EXAMPLE 1
You can click on a variable name in the editor to display all readers and writers, or on a signal in the schematic view to show all sources and destinations.
EXAMPLE 2
The IDE can automatically extract state machine information and generate state diagrams.
EXAMPLE 3
The IDE can filter or show connections of a specific signal or instance, or connections between two or more instances.
EXAMPLE 4
The IDE can display multiple power domains and how they are controlled in a supply-network diagram.
EXAMPLE 5
The IDE can show waveforms as specified by the popular open-source WaveDrom tool.
EXAMPLE 6
The IDE provides project query views that allow you to search for specific information, such as macro ‘define’ and ‘ifdef’ statements, and specific elements such as modules or module ports.
This improves code comprehensibility and maintainability, without changing its functionality. It can also yield better simulation performance and synthesis results.
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EXAMPLE 1
The IDE can rename a port across the entire design hierarchy without any manual tracing of signals.
EXAMPLE 2
The IDE can extract an expression and create a new variable, and extract a section of code and create a new module.
Text editors have no notion of signal connectivity between design files, so they have no model of the complete design. To trace signals, you must do many manual text searches across multiple files. Text editors cannot generate graphical views such as schematics and power supply network diagrams. There is no way that they can provide the same capabilities as DVT IDE.
“I use DVT Eclipse plugin every day, and all this time it has given me an edge when it comes to debugging and understanding the RTL. If you are reading this, don’t hesitate! Go for it! DVT Eclipse is really good!”
Cristian Ramos-Espinoza
Senior Digital Design Engineer
AMIQ EDA provides tools – DVT Eclipse IDE, DVT IDE for Visual Studio Code, DVT Debugger Add-On, Verissimo Linter, and Specador Documentation Generator – that enable design and verification engineers to increase the speed and quality of new code development, simplify legacy code maintenance, accelerate language and methodology learning, improve source code reliability, and automate user documentation. The result is better design and verification code, developed faster and with fewer resources, in a shorter time to market.
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